A multiplier or multiplier may be realized using a parallel design to achieve good performance such as completing a multiplication operation in one or two cycles. Parallel multipliers need a large number of gates which increases production cost. A multiplier may be built using a serial design to reduce the gate count and cost. Serial multipliers are disclosed in German Patent Application Nos. 10 2007 014 808 and 10 2007 056 104. Multiplication is a basic and central data processing step in all kinds of data processing units and applications. There is a general motivation to improve multiplier units for faster operation and reduced complexity. Generally a tradeoff needs to be found between performance and cost.
A multiplier is typically a part of a microcontroller, microprocessor or other digital unit. The multiplier is typically clocked with the system or main processor clock. For both serial and parallel multipliers the critical signal path delay of the combinatorial logic within the multiplier must be shorter than the clock period of the system clock under the worst PVT conditions. In the commonly used term PVT refers to variances in operational rate based upon fluctuation in the production process, known as production spread (P), varying voltage (V) and varying temperature (T). The electronic characteristics and parameters of the devices will vary slightly from one device to another based upon these factors. The worst PVT conditions are a weak production process, a low operating voltage and a high operating temperature.
An electronic device is mostly not operated under these worst case PVT conditions. Thus the performance of the device is generally much higher than under these worst case PVT conditions. A multiplier may thus be implemented having its own clock independent of the system clock. The multiplier may run faster than the system clock and therefore even serial multiplication can be executed in one or two system clock cycles. Since the multiplier performance does not depend on the system clock frequency, the system can be clocked slower than a typical synchronous architecture while maintaining high multiplication performance. This may enable a significant reduction of the system level energy consumption.
The multiplier local clock may be adapted to the critical path delay of the multiplier. In a synchronous digital design with a fixed clock rate, the clock must always as fast as the critical path of the multiplier under worst case PVT conditions. The electronic circuit is generally not operated under these worst case conditions. An adaptive clock may enable the multiplier to be operated faster. This will increase the average performance of the multiplier. However, the multiplier must be as fast as the system requires the respective results from the multiplier. In other words, the local clock of the multiplier must be fast enough (under all PVT conditions) to provide appropriate service to the rest of the system. For example, the multiplier may need one system clock cycle for one multiplication under typical PVT conditions while it may require two system clock cycles under worst case PVT conditions. Thus the system clock speed or the clock frequency of the multiplier has to be adjusted to the current PVT conditions. This required a generally cost and time consuming calibration process which may be required of every device. This calibration compensates for the production spread (P). The voltage (V) and temperature (T) have to be measured during operation of the device in order to properly adjust the clock frequency.